English
全部
搜索
图片
视频
短视频
地图
资讯
更多
购物
航班
旅游
笔记本
报告不当内容
请选择下列任一选项。
无关
低俗内容
成人
儿童性侵犯
时长
全部
短(小于 5 分钟)
中(5-20 分钟)
长(大于 20 分钟)
日期
全部
过去 24 小时
过去一周
过去一个月
去年
清晰度
全部
低于 360p
360p 或更高
480p 或更高
720p 或更高
1080p 或更高
源
全部
Dailymotion
Vimeo
Metacafe
Hulu
VEVO
Myspace
MTV
CBS
Fox
CNN
MSN
价格
全部
免费
付费
清除筛选条件
安全搜索:
中等
严格
中等(默认)
关闭
筛选器
0:19
Python on FPGA: Real-Time Verilog Demonstration! #shorts
已浏览 312 次
8 个月之前
YouTube
quantlabs
2:58
Master SystemVerilog Arrays | Fixed, Packed, Unpacked Arrays Explained with Code
已浏览 50 次
2 个月之前
YouTube
Chip Logic Studio
2:34
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
已浏览 113 次
2 个月之前
YouTube
Chip Logic Studio
2:57
Master SystemVerilog Arrays | Fixed, Packed, Unpacked Arrays Explained with Code
已浏览 164 次
2 个月之前
YouTube
Chip Logic Studio
2:52
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
已浏览 688 次
3 个月之前
YouTube
Chip Logic Studio
1:06
Best Verilog Tools for Beginners | VS Code, Icarus & Vivado #Verilog#VLSI#Vivado#VSCode#FPGA
已浏览 507 次
5 个月之前
YouTube
Silicon Simplified
2:57
Master SystemVerilog Arrays | Fixed, Packed, Unpacked Arrays Explained with Code
已浏览 311 次
2 个月之前
YouTube
Chip Logic Studio
2:31
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
已浏览 126 次
2 个月之前
YouTube
Chip Logic Studio
2:44
Master SystemVerilog Arrays | Fixed, Packed, Unpacked Arrays Explained with Code
已浏览 10 次
1 个月前
YouTube
Chip Logic Studio
2:54
SystemVerilog Associative Array Explained | Code, Testbench & Simulation for Beginners
已浏览 43 次
1 个月前
YouTube
Chip Logic Studio
2:57
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
已浏览 167 次
3 个月之前
YouTube
Chip Logic Studio
2:31
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
已浏览 123 次
2 个月之前
YouTube
Chip Logic Studio
2:57
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
已浏览 88 次
3 个月之前
YouTube
Chip Logic Studio
2:31
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
已浏览 86 次
2 个月之前
YouTube
Chip Logic Studio
3:00
SystemVerilog Associative Array Explained | Code, Testbench & Simulation for Beginners
已浏览 177 次
1 个月前
YouTube
Chip Logic Studio
0:47
How to Start learning FPGAs #vlsi #fpga #verilog
已浏览 2393 次
8 个月之前
YouTube
The Hardware Developer
2:41
conditional statements in verilog | if else & case
已浏览 182 次
4 个月之前
YouTube
Chip Logic Studio
2:51
Verilog Timing Control | Delay Control and Event Synchronization
已浏览 234 次
5 个月之前
YouTube
Chip Logic Studio
2:34
demultiplexer in verilog | rtl design & testbench
已浏览 218 次
4 个月之前
YouTube
Chip Logic Studio
2:54
SystemVerilog Queue Explained | Code, Testbench & Simulation Tutorial
已浏览 132 次
1 个月前
YouTube
Chip Logic Studio
0:50
Claude Code, Verilog and Blink on Nandland Go Board's iCE40HX1K FPGA - 10 Minutes - Incredible!
已浏览 1371 次
6 个月之前
YouTube
Craig Hollabaugh
0:58
Verilog interview preparation || part 1 || #vlsi #verilog
已浏览 47 次
7 个月之前
YouTube
Fluxray Electronics
0:56
Creating an Array with Ascending Values | SystemVerilog Constraint Tutorial #techshorts #shorts
已浏览 1353 次
2024年6月29日
YouTube
PODCAST-with-NAVNEET
0:58
How to Write a Constraint for Setting Diagonal Elements to 1 in SystemVerilog#navneettechshorts#vlsi
已浏览 1850 次
2025年2月19日
YouTube
PODCAST-with-NAVNEET
0:49
You NEED a complete and up to date LinkedIn profile in 2026. LinkedIn is essentially a search engine for recruiters—if your profile doesn’t have the right keywords, you won’t be found or considered for interviews. To fix this, you need to: 🔑 Target Keywords: Add technical skills like (ex. Python, Verilog, or UVM) to your headline, about section, and experience. 🖼️ Build a Portfolio: Don’t just list skills—post photos of your hardware builds or screen recordings of your code. 📄 Pin Your Resume
已浏览 3966 次
5 个月之前
TikTok
engcalebj28
Lộ Trình 6 Bước Trở Thành Kỹ Sư Thiết Kế IC
已浏览 4660 次
2025年4月25日
TikTok
chiptalkglobal
1:00
How to Write a Constraint to Generate the Pattern 000111222333... #shorts #navneettechshorts #vlsi
已浏览 1330 次
2024年8月12日
YouTube
PODCAST-with-NAVNEET
1:56
You NEED a polished and ATS-friendly resume in 2026……. A resume is essentially your first impression with recruiters if yours isn’t optimized with the right structure and keywords, you won’t even make it past the initial screening. To fix this, you need to: 🔑 Use LaTeX: Don’t just use a basic doc!! Templates like Jake’s Resume on Overleaf are highly compatible with ATS and look professional to recruiters. 🖼️ Showcase Projects: Don’t just list titles provide links to your GitHub or portfolios s
已浏览 1253 次
5 个月之前
TikTok
engcalebj28
0:59
How to Write a Constraint to Generate the Pattern 100110011001... #shorts #navneettechshorts #vlsi
已浏览 1356 次
2024年8月16日
YouTube
PODCAST-with-NAVNEET
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL)
已浏览 624 次
4 个月之前
YouTube
Sly Fox electronics
展开
更多类似内容
反馈